1. Field of the Invention
The present invention relates generally to read-only memories (ROMs) and more specifically to a circuit for sensing bits in ROMs.
2. Background Art
Electronic read only memory (ROM) cells are usually organized in a rectangular (x-y) array, and the state of a particular cell is determined by using row decoders to activate a particular wordline (typically in the x direction) and by using column decoders to detect the bitline signal response on the bitlines (typically in the y direction). FIG. 1 shows a memory system 100 including a conventional sense amplifier or current mirror circuit 102 for sensing binary bits ("1" or "0") in a ROM array. Sense amplifier 102 utilizes a conventional single-ended sensing scheme. N-channel current mirror transistors 105 and 110 have drains connected to a first supply voltage potential "Vcc" which is typically at a positive value, and have gates connected to each other. Transistor 110, which is the load transistor, mirrors the current through transistor 105, which is the load mirror transistor. Transistors 105 and 110 may ratio current such that the current through transistor 110 is, for example, twice the current through transistor 105. A predetermined ratio may be realized by the conventional practice of forming the respective source-drain paths of transistors 105 and 110 with proper relative dimensions.
An inverter 115 has an input terminal connected to the source of transistor 105 and has an output terminal connected to the gates of transistors 105 and 110. Inverter 115 includes p-channel transistor 120 and n-channel transistor 125. Transistors 120 and 125 have their gates connected together and to the source of n-channel transistor 105, and have their drains connected together and to the output of inverter 115. P-channel transistor 120 has its source connected to Vcc, while n-channel transistor 125 has its source connected to a second supply voltage potential Vss which is typically at ground.
ROM bit cell 130 is typically an n-channel transistor with its gate connected to a wordline 135, its drain connected to the source of n-channel transistor 105 and its source connected to Vss. Reference cells 140 and 145 (typically n-channel transistors) have their gates connected to Vcc. The source of reference cell 140 is connected to the drain of reference cell 145. The source of reference cell 145 is connected to Vss, while the drain of reference cell 140 is connected to the source of n-channel transistor 110 and to the input terminal of amplifier 150. Amplifier 150 has an output terminal connected to digital circuitry 155, typically bus drivers, a data bus or output registers. Sense amplifier 102 can sense the state of a data bit stored in ROM bit cell 130 and accordingly output a digital signal representing the value of the stored data bit.
Sense amplifier 102 has the disadvantage of losing speed or functioning capability when the Vcc voltage level falls to two transistor threshold voltage levels or 2 V.sub.T. Thus, when Vcc falls to a low voltage level, e.g., 1.2 volts, sense amplifier 102 is unable to sense ROM bits.
Additional bitline sensing circuits in a memory array are disclosed in U.S. Pat. Nos. 4,541,077, 5,297,093 and 5,619,449, which are fully incorporated herein by reference. Current mirror circuits are further discussed in Horowitz, Paul and Hill, Winfield, The Art Of Electronics (2nd ed.), Cambridge University Press, New York, N.Y. (1996), which is fully incorporated herein by reference.
There remains a need for a circuit and method for sensing ROM bits at low supply voltage levels.